Nowadays, internet of things (IoT) and portable devices require the necessity to implement fast and low-power machine learning (ML) techniques in a single integrated circuit (IC) since both power dissipation and process latency are drastically reduced when only high-level information is transmitted from nodes to servers instead of basic raw data. From the different machine learning techniques, artificial neural networks (ANNs) has gained a lot of attention from industry mainly due to the accuracy obtained when solving real-life problems such as image or sound recognition, which normally implies the processing of huge amounts of information. Therefore, there has been a growing interest from the microelectronics industry to implement different artificial intelligence (AI) processes in a single IC.
A Spanish university research group, working in the area neural networks, proposes a new methodology for the hardware implementation of large artificial neural networks based on probabilistic laws. The research group uses advanced techniques based on the use of stochastic computing concepts that allow important hardware reductions as complex computations may be reproduced by a reduced set of digital gates compared to traditional binary logic. With these techniques, large neural networks can be reproduced by the automatic generation of its hardware description code (normally VHDL). Along with the VHDL source codes, detailed technical documentation and training software will be provided for its proper use. Previously, field-programmable gate array (FPGA) implementation demos can be delivered to the potential customers for their evaluation. Those machine learning techniques can be used for both regression and pattern recognition.
A technical cooperation agreement is desired for the implementation of the proposed technology in the areas of finance, security or others.